[Roccc-discussion] System code compilation

[Jason Villarreal]

>   Dear Jason, Dear all,
> 
>   I'm carrying out some experiments on C-to-VHDL compiling using
> ROCCC and I wanted to ask a question about the compilation of
> System code.
> 
>   I assume that the variables in System code that are written but not
> read - let's say leaf nodes in the data flow graph - eventually become
> output ports in the generated VHDL entity. Let's take as
> an example the B array in the FIR-system example. If so, why does the
> i variable in the cited example appear in the generated VHDL as
> output port? I found that in the previous version of ROCCC, the 0.3
> one, this does not happen, and the component declaration of the
> FIR-system module in the testbench code doesn't show that output port
> as well.
> 
>   I'd be grateful if you could help me.
> 
>   Kind regards,
> 
>   --
> Giuseppe Cascone
> 
> Ph.D. Student

For every array identified as an output stream, we generate the indices associated with each valid output value and output them in addition to the output data.  The I variable in the cited example is such an index.  This can be used by any wrapper interface to generate addresses as appropriate, but it could be ignored.  An array is identified as an output stream if it is written to and not read from.

For scalar variables to be identified as an output variable and have an output port associated with them in the generated VHDL we will identify all variables that have a definition but no following use in the innermost loop (and are not identified as feedback variables - variables that are read first and then written in the innermost loop).  The generation of these ports for scalars is currently being developed for the next bugfix release.

Thanks,
Jason